1. Field of the Invention
The present invention relates to the field of computers. More specifically, the present invention relates to computer architecture.
2. Description of the Related Art
Conventional multi-processor systems attempt to take advantage of faster access of cache than memory. When a processor generates a cache miss, the cache miss is broadcast to other processors of the system. The other processors monitor the system bus for such communications (“snooping”). If a processor snoops a cache miss on the system bus, then the processor queries its own cache to determine if the desired data resides within its cache. Typically, a snooping mechanism, coextensive with a bus controller, issues a “snoop” to the cache. In order to maintain cache coherency, snoops and snoop responses abide by sequential constraints. Conventional processors maintain a queue for the snoops and the snoop responses. The queues force the snoops and snoop responses to conforms to the sequential constraints for cache coherency.
However, conventional techniques do not account for snoops initiated internally and externally with respect to a processor. Asynchronous snoop arrival from the system and internal cache activity of a processor violates the desired sequential constraints. Replication of the conventional technique which accommodates a single secondary cache within a processor, would employ a port for each second cache. In addition to increasing complexity and occupation of space with additional ports, the number of snoop responses would increase, thus forcing the system bus to handle additional traffic.